Field of the Invention
The present invention relates to a method for checking the functioning of memory cells of an integrated semiconductor memory.
Various test methods are known for checking memory cells of an integrated semiconductor memory with regard to their functional capability. During such a test mode for checking memory cells, by way of example, test data are written to each individual memory cell and read out again. A comparison between the written data and the data read out again provides information about whether or not a functional error is present.
In order, during such functional checking, which requires the transfer of large volumes of data, not to be restricted in the data transfer rate by the number of available memory connections, it is likewise known to provide a test circuit that carries out the functional checking on the same integrated circuit on which the memory is situated. Such a realization, also referred to as a xe2x80x9cbuilt-in self testxe2x80x9d (BIST), can be gathered from Published, Non-Prosecuted German Patent Application DE 197 25 581 A1. The method described therein provides for only a first group of the memory cells of the integrated memory to be tested and the test results obtained in the process to be buffer-stored in a second group of the memory cells before they are output to a point outside the memory. If both groups are part of a common memory, this results in that the instant at which the test results are output is independent of their generation and the functional checking can be carried out more quickly. In order, for storing the test results, not to have to provide an additional memory which, for example, is part of the test circuit, the test results are buffer-stored in the second group of the memory cells, which is likewise to be tested. Since the latter memory cells have not yet been subjected to functional checking, errors are possible during the buffer-storage of the test results. These can be avoided by using an error correction code, for example, during the buffer-storing of the test results. Errors occurring during buffer-storage are thereby detected, and if appropriate corrected, during the read-out and evaluation of the test results from the memory cells.
A described error correction method makes use of the method of buffer-storing the test results in each case in multiple embodiment in the memory cells of the second group and of performing a comparison between the copies of each of the test results during the read-out of the test results. That value which occurs most often within the copies during the read-out from the memory cells is regarded as the xe2x80x9ccorrectxe2x80x9d test result. However, such a method functions reliably only when, in an error-affected memory cell array, a plurality of functional errors that occur are distributed statistically identically, that is to say no significant cluster of functional errors can be ascertained. In this connection, reliable methods that the error correction method obtains a correct test result with the likelihood originally intended for it.
In an error-affected memory cell array in which the memory cells are connected to a respective row line and column line, by contrast, when multiple functional errors occur, significant clusters of the functional errors can be ascertained along column lines or row lines. Thus, in the case of a defective sense amplifier, for example, the row or column line connected to the sense amplifier is affected in terms of its functional capability, and thus so are all the memory cells connected thereto. If the copies of a test result are stored on successive memory cells along a row or column line, in such a case all the copies are affected by a functional error and the xe2x80x9ccorrectxe2x80x9d test result can no longer be reconstructed by majority decision.
It is accordingly an object of the invention to provide a method for checking the functioning of memory cells of an integrated semiconductor memory which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which an error correction method based on majority decision can be reliably employed.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking the functionality of an integrated semiconductor memory. The method includes testing a first group of memory cells resulting in test results and buffer storing the test results, separately for each tested memory cell, in at least triple copies in a second group of the memory cells. A comparison between the copies of each of the test results is then performed. Information about a functional capability of the memory cells of the first group is determined in a manner dependent on the comparison of the copies. The memory cells are accessed by use of addresses. The addresses of the memory cells contain a first address part through which one of the first group and the second group of the memory cells is accessed, and a second address part through which the memory cells within one of the first group and the second group are accessed. The addresses of each the memory cells contain a number of address bits, and the second address part of a memory cell of the second group is generated, proceeding from a corresponding second address part of a respectively tested memory cell of the first group by an address transformation by alteration of at least one of the address bits.
The method according to the invention provides for a first group of memory cells to be tested and then the test results to be stored in at least triple embodiment in the memory cells of a second group. The addresses or parts of the addresses of the memory cells in which the copies of one of the test results are stored are determined, proceeding from a corresponding part of the address of the tested memory cell, by an address transformation. The address transformation is configured in such a way that significant clusters of functional errors in an as yet untested, error-affected second group of the memory cells do not influence the result of the test method. Consequently, even without knowledge of specific error patterns (clusters of functional errors) of individual types of semiconductor memories, reliable functional testing can be effected, or, by the address transformation, the influence of a known specific error pattern of a memory on the error correction method, which is based on a statistical uniform distribution of functional errors, can be rendered ineffectual.
One embodiment provides for address bits of the addresses of the respective memory cells of the second group in which the copies of one of the test results are stored to be combined with one another. Thus, a sequence of addresses, for example a linear sequence, is transformed into a random sequence. The fact that the memory cells with the copies of a test result are randomly distributed over the memory cell array of the second group results in that clusters of functional errors do not affect the result of the error correction method. Knowledge of a specific error pattern that is respectively present is not necessary.
Another embodiment is based on the fact that functional errors in an error-affected memory with memory cells that are connected to a respective column line and row line cluster along precisely these column and row lines. In order to obtain the xe2x80x9ccorrectxe2x80x9d test result from the memory cells of the second group by a majority decision, the memory cells with the copies of a test result are disposed in such a way that their column addresses and row addresses differ. In other words, functional errors along a column line or row line only ever relate to one copy of a test result and the xe2x80x9ccorrectxe2x80x9d test result can be reconstructed by the majority.
Further-reaching embodiments specify how the test results are distributed over the memory cell array of the second group, namely at mutually identical address spacings, and how the corresponding addresses or address parts are determined.
In accordance with an added mode of the invention, the integrated semiconductor memory has column lines and row lines. The memory cells are each connected to a respective one of the row lines and a respective one of the column lines and the addresses are decoded in a column address decoder and a row address decoder. The method further includes the step of determining an address of the memory cell of the second group storing a copy of a test result using a spacing value being added to the second address part of the respectively tested memory cell of the first group, so that the column addresses and row addresses of the memory cells of the second group with the copies of one of the test results differ.
In accordance with an additional mode of the invention, there is the step of disposing the memory cells of the second group in which the copies of one of the test results are stored, at mutually identical address spacings.
In accordance with another mode of the invention, there is the step of setting the spacing value in a variable manner at the beginning of the functional checking.
In accordance with a further mode of the invention, there is the step of setting the second address part of the address of the memory cell of the second group which contains a first copy of the test result to be identical to a corresponding second address part of the address of the respectively tested memory cell of the first group. And, proceeding from the second address part of the address of the memory cell, the addresses of the memory cells which contain the other copies of the test result are determined.
Although the invention is illustrated and described herein as embodied in a method for checking the functioning of memory cells of an integrated semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.